慧榮科技
Silicon Motion Technology Corporation
慧榮科技是專精NAND Flash快閃記憶體控制晶片的IC設計公司,2005年在美國Nasdaq上市,我們在全球Merchant SSD及Merchant eMMC/UFS控制晶片市場居於領導地位。目前於竹北、新店、中國、香港、韓國、日本、美國等地均設有研發及營運團隊。
| 公司名稱 | 慧榮科技股份有限公司 |
| 公司類別 | 製造業-半導體 |
| 公司電話 | 03-5526888 |
| 公司地址 | 302 新竹縣竹北市復興三路二段162號 |
| 職缺內容 | 對IC設計產業有熱忱,並不安於平凡,且渴望學習成長的青年學子,歡迎您加入慧榮大家庭。 |
| 應徵方式 | 請至104查詢求才資訊,並歡迎線上登錄履歷。 |
| 名稱 | 數量 | 內容 | 學歷條件 | 薪資待遇 | 福利制度 | 休假制度 | 備註 |
|---|---|---|---|---|---|---|---|
| 類比IC設計工程師 Analog IC Design Engineer | 5 | 1. Analog ip top integrated, including project of SSD/UFS/eMMC/SD … 2. Basic analog circuit design concept about LDO/DCDC/BANDGAP/Voltage Detector or PLL/ADC…etc. 3. Help to do fail sample analysis & IC measurement. 1. Analog ip top integrated, including project of SSD/UFS/eMMC/SD … 2. Basic analog circuit design concept about LDO/DCDC/BANDGAP/Voltage Detector or PLL/ADC…etc. 3. Help to do fail sample analysis & IC measurement. | 1. Familiar with Spice、Matlab 2. Mass production know-how/experience is better 3. Basic analog circuit design concept about LDO/DCDC/BANDGAP/Voltage Detector or PLL/ADC...etc 1. Familiar with Spice、Matlab 2. Mass production know-how/experience is better 3. Basic analog circuit design concept about LDO/DCDC/BANDGAP/Voltage Detector or PLL/ADC...etc | ||||
| 數位IC設計工程師 Digital IC Design Engineer | 10 | 1. RTL/Digital circuit design, synthesis, and simulation/verification. 2. FPGA synthesis, verification. 1. RTL/Digital circuit design, synthesis, and simulation/verification. 2. FPGA synthesis, verification. | 1. Familiar with Verilog / RTL coding 2. Familiar with Synopsys / Cadence / front-end design flow 3. Familiar with FPGA HW & SW integration 1. Familiar with Verilog / RTL coding 2. Familiar with Synopsys / Cadence / front-end design flow 3. Familiar with FPGA HW & SW integration | ||||
| 韌體設計工程師 Firmware Design Engineer | 30 | 1.SSD/eMMC/UFS controller firmware design, customization and customer support. 2.SATA/PCIe protocol firmware design. 1.SSD/eMMC/UFS controller firmware design, customization and customer support. 2.SATA/PCIe protocol firmware design. | 1. Familiar with C / C++ / Assembly coding 2. Familiar with ARM based MCU 1. Familiar with C / C++ / Assembly coding 2. Familiar with ARM based MCU | ||||
| 實體設計(APR/CAD)工程師 Physical Design Engineer | 5 | APR/Physical design (P&R), including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout. APR Physical design (P&R), including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout. | 1.Familiar with Synopsys/Cadence backend APR design flow. 2. Hand on APR physical design from netlist to GDS (PV clean) tapeout experience is better. 1.Familiar with Synopsys/Cadence backend APR design flow. 2. Hand on APR physical design from netlist to GDS (PV clean) tapeout experience is better. |